With much talk about some PCIe x16 ports only supporting lesser bus widths when used with non-graphics cards, I've been attempting to discover what bus width my LSI2008 controller is actually achieving in my Intel DH55TC mobo.

 

When I look at dmesg, I can see that the e1000e driver reports 'x1', but the mptsas2 driver doesn't appear to report this information.  Where should I look for confirmation of the negotiated bus width?

#Where should I look for confirmation of the negotiated bus width?

 

run:

 

lspci -vv

 

as root.  LinkSta shows the current link status, LinkCap show the max the device is capable of...

 

Tim.

#Where should I look for confirmation of the negotiated bus width?

 

lspci -vv

 

LinkSta shows the current link status, LinkCap show the max the device is capable of...

 

Thanks for the reply.

 

		LnkCap:	Port #0, Speed 5GT/s, Width x8, ASPM L0s, Latency L0 <64ns, L1 <1us
		ClockPM- Suprise- LLActRep- BwNot-
	LnkSta:	Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-

 

So the card is, indeed, working at full capacity.  With all the stories about 'graphics PCIe slots' working at less than optimal capacity, it's good to know that my Intel mobo is well behaved.