CyrIng

This is the commit of master branch which fixes i5-12500 monitoring. @ich777 can you confirm if that change is part of the plug-in ?

@ich777 Version 1.91.7 is fixing the Monitoring issue with Pcores only Alder Lake

Marvelous I'm now preparing this hotfix for CoreFreq 1.91.7

Now CoreFreq is stuck Please reboot from USB key; abort auto compilation Go to /opt/CoreFreq And apply the source code changes in corefreqk.c (see above) Make and Run

nano corefreqk.c ## go to function Start_Alderlake at lines 16751 ## in the switch statement you will find 3 case which starts Pcore monitoring ## you will add a default condition below these cases, like: case Hybrid_Core: case Hybrid_RSVD1: case Hybrid_RSVD2: default: SMT_Counters_Alderlake_Pcore(Core, 0); ## You will do the same in function InitTimer_Alderlake at lines 16737 case Hybrid_Core: case Hybrid_RSVD1: case Hybrid_RSVD2: default: smp_call_function_single(cpu, InitTimer, Cycle_Alderlake_Pcore, 1); Save changes pressing [F3] and exit nano with [2] Then you rebuild CoreFreq make clean all Stop the Daemon if it's still running with "kill %1" and unload driver with "rmmod corefreqk.ko" Now you start CoreFreq from this fresh build.

@chchiyan At any time, you can paginate a single output with "less" like: corefreq-cli -s | less

Good! we have data but is the monitoring loop working ? Can you now enter "corefreq-cli -c 3"

Check syntax of driver name. Try again with: insmod corefreqk.ko ServiceProcessor=0 Next starts Daemon in background mode: ./corefreqd -q & And dump Processor information using CLI: ./corefreq-cli -s -n -m EDIT: Before entering the above commands, it would be easier to boot from a plain shell. This will avoid the messed terminal you have encountered. While the ISO is loading, when you are asked to abort, press [Ctrl]+[c] to go straight to the shell. Change then to /opt/CoreFreq and do a "make" And continue with CoreFreq starts commands

@chchiyan What's new for CoreFreq is that i5-12500 has no E-core I think the early CPU topology built by driver is messed up. You may a chance to start driver by binding the Service Processor to a P-core. Let's try to bind to first CPU : "insmod corefreq.ko ServiceProcessor=0" Then starts Daemon and CLI.

Please exit CLI to go back to shell then check for any driver crash using "dmesg" CoreFreq is in directory /opt You can "make" and just "insmod corefreq.ko" from it. Then read "dmesg" immediately for any crash.

Please exit CLI to go back to shell then check for any driver crash using "dmesg" CoreFreq is in directory /opt You can "make" and just "insmod corefreq.ko" from it. Then read "dmesg" immediately for any crash.

Messages seems linked to file system errors : is the USB key of good quality ? Or the downloaded image corrupted ? You can also boot any other Linux with kernel development kit and build/try CoreFreq from it. I have preliminary reports of Alder lake, most "k" models have been tested/enhanced. See CPU Support page within the CoreFreq Github repo.

Hello, I have checked your logs/syslog.txt for a possible driver crash, but don't find any. Do you mind to try my ISO ? https://github.com/cyring/CoreFreq/wiki/Live-CD

Kernel 5.19 and Ryzen 3950X with amd_pstate enabled The ACPI CPPC is involved: per CPU, the target ratio is scaling from a min of 5 up to a max linked to CPB boosted ratio. WiP: studying the amd_pstate source code; CoreFreq (development branch) can now alter the CPPC target ratio. CPPC firmware has to be enabled : press same UI button as HWP. See progress in this post

Es ist blau, weil CPPC von Firmware verwaltet wird; und nicht von MSR-Registern Die 5000-Serie wird grün sein. Und die Verhältnisse können geändert werden. (Traduit du français)

Indeed blue means capable, and green, enabled. In your case CPPC is capable but not in function. You can enable it in window "Performance Monitoring", item "Collaborative Processor Performance Control" Remarks: CPPC appears to be a firmware implementation, I can't tell what BIOS is going to do when enablement bit is set.

One will need to unload any running cpufreq driver before attempting to register CoreFreq. Those mainstream driver names depends on processor model (acpi, amd_pstate,...) CLI can display current drivers See Readme, Wiki, of project.

You will observe a visual difference when running in Console or Xterm

For your testings are available 2 new startup parameters: * Ratio_Boost * Ratio_HWP Pull develop branch at https://github.com/cyring/CoreFreq/tree/develop For example: insmod corefreqk.ko Ratio_Boost=-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10,24 TurboBoost_Enable=0,1 Which means, from Turbo ratio 18C down to 1C, value -1 keep current hardware ratio, other positive is your new Turbo frequency ratio Special case of AMD/Zen: Parameter TurboBoost_Enable=0,1 means value 0 at first to disable Turbo and allow changing P-State ratio from list Ratio_Boost ; at second, value 1 means restore Turbo after changed. This is not required with Intel.

Thanks for using CoreFreq. Noticing that dim grey color is not showing up in the screenshots : can you tell which Terminal is used or if the colors palette was changed from Linux standard ?

Thanks for the log. I found the issue: Spinlock invoked from hrtimer handler

corefreq.cfg has been made for the UI purpose only. Mainly that file will save the windows disposal. Features involving Processor are not saved at any time. After tuning processor, you decide to associate safe values to the driver parameters as permanent startup settings. Remark: so far Turbo Boost ratios are not available as driver parameter. All parameters can be listed using the Linux command modinfo Next you'll set "parameter=value" list in file /etc/modprobe.d/modprobe.conf modinfo corefreqk filename: /lib/modules/5.19.0-rc2-1-mainline/kernel/drivers/misc/corefreqk.ko version: 1.92.0 license: GPL description: CoreFreq Processor Driver author: CYRIL INGENIERIE <labs[at]cyring[dot]fr> srcversion: 3D9694DC2223B90FADF93D5 depends: retpoline: Y name: corefreqk vermagic: 5.19.0-rc2-1-mainline SMP preempt mod_unload parm: ArchID:Force an architecture (ID) (int) parm: AutoClock:Estimate Clock Frequency 0:Spec; 1:Once; 2:Auto (int) parm: SleepInterval:Timer interval (ms) (uint) parm: TickInterval:System requested interval (ms) (uint) parm: Experimental:Enable features under development (int) parm: CPU_Count:-1:Kernel(default); 0:Hardware; >0: User value (int) parm: Target_Ratio_Unlock:1:Target Ratio Unlock; 0:Lock (short) parm: Clock_Ratio_Unlock:1:MinRatio; 2:MaxRatio; 3:Both Unlock (short) parm: Turbo_Ratio_Unlock:1:Turbo Ratio Unlock; 0:Lock (short) parm: Uncore_Ratio_Unlock:1:Uncore Ratio Unlock; 0:Lock (short) parm: ServiceProcessor:Select a CPU to run services with (int) parm: RDPMC_Enable:Enable RDPMC bit in CR4 register (ushort) parm: NMI_Disable:Disable the NMI Handler (ushort) parm: Override_SubCstate:Override Sub C-States (array of ushort) parm: PkgCStateLimit:Package C-State Limit (short) parm: IOMWAIT_Enable:I/O MWAIT Redirection Enable (short) parm: CStateIORedir:Power Mgmt IO Redirection C-State (short) parm: Config_TDP_Level:Config TDP Control Level (short) parm: Custom_TDP_Offset:TDP Limit Offset (watt) (array of short) parm: PowerTimeWindow:Power Limit PL(n) Time Window (array of short) parm: Activate_TDP_Limit:Activate TDP Limiting (array of short) parm: Activate_TDP_Clamp:Activate TDP Clamping (array of short) parm: Custom_TDC_Offset:TDC Limit Offset (amp) (short) parm: Activate_TDC_Limit:Activate TDC Limiting (short) parm: L1_HW_PREFETCH_Disable:Disable L1 HW Prefetcher (short) parm: L1_HW_IP_PREFETCH_Disable:Disable L1 HW IP Prefetcher (short) parm: L2_HW_PREFETCH_Disable:Disable L2 HW Prefetcher (short) parm: L2_HW_CL_PREFETCH_Disable:Disable L2 HW CL Prefetcher (short) parm: SpeedStep_Enable:Enable SpeedStep (short) parm: C1E_Enable:Enable SpeedStep C1E (short) parm: TurboBoost_Enable:Enable Turbo Boost (short) parm: C3A_Enable:Enable C3 Auto Demotion (short) parm: C1A_Enable:Enable C3 Auto Demotion (short) parm: C3U_Enable:Enable C3 UnDemotion (short) parm: C1U_Enable:Enable C1 UnDemotion (short) parm: CC6_Enable:Enable Core C6 State (short) parm: PC6_Enable:Enable Package C6 State (short) parm: ODCM_Enable:Enable On-Demand Clock Modulation (short) parm: ODCM_DutyCycle:ODCM DutyCycle [0-7] | [0-14] (short) parm: PowerMGMT_Unlock:Unlock Power Management (short) parm: PowerPolicy:Power Policy Preference [0-15] (short) parm: Turbo_Activation_Ratio:Turbo Activation Ratio (short) parm: PState_FID:P-State Frequency Id (int) parm: PState_VID:P-State Voltage Id (int) parm: HWP_Enable:Hardware-Controlled Performance States (short) parm: HWP_EPP:Energy Performance Preference (short) parm: HDC_Enable:Hardware Duty Cycling (short) parm: EEO_Disable:Disable Energy Efficiency Optimization (short) parm: R2H_Disable:Disable Race to Halt (short) parm: Clear_Events:Clear Thermal and Power Events (ullong) parm: ThermalPoint:Thermal Point (array of short) parm: PkgThermalPoint:Package Thermal Point (array of short) parm: ThermalScope:[0:None; 1:SMT; 2:Core; 3:Package] (int) parm: VoltageScope:[0:None; 1:SMT; 2:Core; 3:Package] (int) parm: PowerScope:[0:None; 1:SMT; 2:Core; 3:Package] (int) parm: Register_CPU_Idle:Register the Kernel cpuidle driver (short) parm: Register_CPU_Freq:Register the Kernel cpufreq driver (short) parm: Register_Governor:Register the Kernel governor (short) parm: Register_ClockSource:Register Clock Source driver (short) parm: Idle_Route:[0:Default; 1:I/O; 2:HALT; 3:MWAIT] (short) parm: Mech_IBRS:Mitigation Mechanism IBRS (short) parm: Mech_STIBP:Mitigation Mechanism STIBP (short) parm: Mech_SSBD:Mitigation Mechanism SSBD (short) parm: Mech_IBPB:Mitigation Mechanism IBPB (short) parm: Mech_L1D_FLUSH:Mitigation Mechanism Cache L1D Flush (short) parm: Mech_PSFD:Mitigation Mechanism PSFD (short) parm: WDT_Enable:Watchdog Hardware Timer (short) parm: HSMP_Attempt:Attempt the HSMP interface (short) I will come back with the Turbo Boost ratios ability.

@CameraRick Hello, Using you Ryzen model Cezanne, can you read that MSR and post value here or better at the project issue: rdmsr -ax 0xc0002075 and this one (according to model PPR) rdmsr -ax 0xc0002005

EDIT: The root cause is that I'm missing the base address of the Cezanne memory controller. See project issue AMD/Zen3/Cezanne UMC base address is unknown

Hello, Using an AMD Zen processor, CoreFreq is incompatible with any monitoring tool running in parallel. CyrIng